1. Field of the Invention
This invention relates to signal integrity analysis of a digital electronic circuit and more particularly to providing comprehensive stimulus for efficient signal integrity simulation of electronic circuits.
2. Description of the Related Art
In an integrated circuit design process, electronic circuits such as integrated circuit devices (ICs) are simulated to verify design accuracy. Stimulus patterns are provided at the inputs to the IC and the results are verified at the outputs of the IC. When designing a system, multiple ICs are connected together on a printed circuit board (PCB) via signal traces. Simulation of an electronic system, for example, a having large amounts of signal traces connecting multiple integrated circuit devices (ICs), is a complicated and time consuming process. Often, the characteristics of the signal traces are simply ignored or estimated with resistance-capacitance (RC) delay and the simulation of the electronic system focuses on the interaction of the outputs of the ICs. This treatment of signal traces in system simulation was acceptable in the past because clock speeds were slow and PCB population was not dense.
The signal integrity of signal traces has become increasingly important as digital signal rates in electronic systems have increased. At higher frequencies, PCB traces can no longer be treated as just wires used to connect ICs together. Instead, the PCB traces must be treated as radio frequency (RF) transmission lines. At high-speeds PCB traces, as well as connectors and IC packages, can make up a significant part of the overall signal delay. Even worse, interaction between signal traces can cause glitches, resets, logic errors, and other problems. Thus, verification of the correct functioning of high-speed digital hardware involves both digital design to verify proper operation of ICs and analog circuit design to verify proper operation of the signal traces between ICs.
Signal integrity analysis of network interconnections includes analyzing both transmission line effects such as ringing and reflections and interaction between signal traces, such as cross talk and simultaneously switching output (SSO) noise on the power planes. Signal characteristics can change over time due to these effects. Crosstalk between signals increases proportionally to the clock rate and can cause data dependent logic errors. Ground bounce and power supply noise increases with higher-powered drivers, increased switching rates, and parallel bus structures. Signal wave shape and propagation delay is also very important at high speeds. Careful consideration of these effects during the design process leads to robust system-level performance and reliability.
As system bus speeds increase, impedance matching on the interconnection network becomes more important. A greater percentage of PCB traces require termination. Terminators help control the signal wave shape on transmission lines. However, terminators occupy precious space on PCBs, and dissipate large amounts of power. More complex busses, such as double data rate (DDR-II) memory devices and advanced graphics port (AGP 8X) devices, implement active termination on-silicon in the I/O circuitry. On-silicon termination is dynamically controlled and saves PCB real estate. Timing associated with activation/de-activation of the dynamic termination circuitry must be carefully controlled in some applications.
Digital simulators have enabled logic design and verification for many years. However, digital simulators do not support analysis of analog characteristics such as transmission line effects and the interaction between PCB traces in a system. Analog simulators such as HSPICE can provide some analog analysis of signals, but provide results only as good as the input stimulus and noise model. For simple systems, where signal integrity is not an issue, delay can be roughly estimated as RC in nature and entered as an input into a logic simulator to model bus performance. For high speed digital systems, however, analog characteristics are not estimated, but rather should be included as part of the simulation to account for the complex interactions between bussed devices. Not only should the length and placement of signal traces be accounted for, but the complex signal transitions, for example, transitions related to bus protocol, on multiple signal traces should be simultaneously analyzed in a noise simulation model. Design cycles are short and the vast number of possible interactions between signal traces has typically made signal integrity analysis too expensive in time and labor to complete thoroughly. Signal integrity noise analysis performed with signal patterns that do not occur in the bus protocol run the risk of over-estimating signal integrity problems the system will experience in actual operation. Alternatively, to reduce signal integrity problems, system designers can place very strict routing and length requirements on signal traces and slow down bus interfaces or insert extra wait cycles to allow signals to settle between bus transactions.
If accurate signal integrity analysis were available prior to system production, improved PCB and I/O targets could be specified prior to design.